Semiconductor packaging is the process of processing wafers that have passed testing into independent chips, covering core processes such as slicing, mounting, bonding, encapsulation, rib cutting, and finished product testing. Its main purpose is to protect the grains from physical damage and impurity corrosion, and meet the appearance requirements of different application scenarios. During the packaging process, the chip needs to be mounted onto the lead frame, connected to the chip pads and substrate pins through metal wires or conductive resin, and protected by a shell packaging. The downstream applications of this technology cover the fields of wearable devices, consumer electronics, and industrial Internet of Things.
Traditional packaging uses lead frames as carriers, including through-hole insertion type packaging (TO, DIP) and surface mount type packaging (SOP, SOJ, TSOP) [5], while advanced packaging technologies include wafer level packaging based on 12 inch wafers (FoWLP), Chiplet technology (integrated bump manufacturing, Fan out, and 2.5D/3D packaging), as well as flip chip bonding (FCB), system level packaging (SiP), and other forms. The industry uses AI visual inspection equipment to automate the screening of defects such as scratches and short circuits, improving product reliability. The development stages of packaging technology can be divided into two major routes: traditional packaging (mainly through-hole insertion packaging and surface mount packaging) and advanced packaging (CSP, WLP, 3D packaging, etc.)
